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In this section, we discuss speed/area trade-offs of parameter variances based off of a Xilinx Spartan-3 implementation. All variances were performed with the same code base with only the parameter de nitions as independent variables. Table 13.3 shows the effects of varying both the width of the data path (WORDSIZE) and the number of input words (WORDNUM). The implementation results in Table 13.3 illustrate the vast difference small parameterizations can make. The rst parameter, WORDNUM, made very little difference as it simply adjusts the number of inputs that are initially muxed into the message schedule. This should add very little overhead as it will only impact a comparison and multiplex operation. The second parameter WORDSIZE, on the other hand, directly impacts the data path of the entire design. In this case, doubling the word size will effectively double the total number of resources required to implement this design.

Separation Theorems on the Common Torus. (See Section 5.8.4). The purpose of this subsection is to prove Theorem 5.8.4. The proof for its planar counterpart can be found in Ref. 110, VI.16.2, which uses the concept of regular grating as the fundamental tool. We will use an analogous strategy to prove Theorem 5.8.4. Since the topology of a torus is different from that of a plane, we start with the modi ed de nitions of regular grating, k-chains, and kcycles in torus T 1 , and proceed with the corresponding operations and properties (Theorems 5.9.1 to 5.9.7). Several intermediate results are needed in order to prove Theorem 5.8.4. The proofs for some of these are the same as their planar counterparts, in which case we simply restate the statements and cite the source [110]. Proofs will be given to statements that are valid only for T 1 . Regular grating is a convenient tool for studying the connectivity of a subset of T 1 . We show in Theorem 5.9.8 that a 1-cycle (a simple closed curve) does not necessarily separate a torus into two halves as it would in a plane. This major fact makes the proof of Theorem 5.8.4 different from its planar counterpart. Finally, to prove Theorem 5.8.4 we need to show that if a region (a connected subset) D in T 1 is uniformly connected, then the connectivity of any of its boundary components is destroyed by the removal of two single points. This is done by drawing a cross-cut L connecting the same boundary component of D and showing that D-L has exactly two components (Theorem 5.9.12). The proof of Theorem 5.9.12 in turn requires the intermediate results of Theorems 5.9.9 to 5.9.11.

Regular Grating. Let us represent T 1 as a unit square with its opposite sides, marked by a and b respectively, identi ed. A regular grating G in T 1 is formed by drawing a nite number of lines parallel to a or b. The lines become closed curves after the identi ed sides are glued together (see Figure 5.41). A grating must contain at least two lines, a and b, that cut the torus surface into a rectangle. The 2-cells of G are the closures of the rectangular regions into which the unit square is divided. The edges, or 1-cells, are the sides of the 2-cells, and the vertices, or 0-cells, are their corners. All cells are bounded closed sets of points. When G contains a and b and at least another two lines that are parallel to a and b respectively, such as the case in Figure 5.41, then every edge of the grating evidently belongs to just two 2-cells, which lie on the opposite sides of it.

Although reducing the supply voltage is usually not a desirable option, it is worth mentioning due to the dramatic effect it can have on power consumption. Power dissipation in a simple resistor will drop off with the square of the voltage. Thus, signi cant power savings can be achieved by lowering the power supply voltage of the FPGA near the minimum required voltage. It is important to note, however, that lowering the voltage will also decrease the performance of the system. If this method is used, ensure that the timing analysis takes into consideration the lowest possible voltage on the supply rail for worst-case maximum timing.

Theorem 5.9.1. If F1 and F2 are nonintersecting closed sets in T 1 , there exists a grating G no cells of which meet both F1 and F2 . Proof: The nonintersecting compact sets F1 and F2 in T 1 are at positive distance apart. Let m be an integer exceeding 4/ . A grating with the required property can evidently be formed by drawing m equidistant straight lines between, and parallel to, each pair of the opposite sides of the unit square. Q.E.D. A k-chain, C k (k = 0, 1, 2), on grating G is any set of k-cells of G. The sum k k (modulo 2) of two k-chains, C1 and C2 , is the set of k-cells that belong to one k k k k and only one of C1 and C2 . It is denoted by C1 + C2 . The complement (C 2 ) 1 2 of a 2-chain C is the set of 2-cells of G not belonging to C 2 . Thus, if 2 denotes the 2-chain containing all the 2-cells of G, (C 2 ) 1 = C 2 + 2 .