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Note that the four corners are identi ed as a single point Without loss of generality, let the start and target points S and T be respectively in the center and the corners of the square This produces four straight lines connecting S and T , each connecting the center of the square with one of its corners We call each line a generic path and denote it by gi , i = 1, 2, 3, 4 De ne a connectivity graph G on the torus by the obstacle-free portions of any three of the four generic paths and the obstacle boundary curves We have the following statement: Theorem 6313 On a torus, if there exists an obstacle-free path connecting two points S and T , then there must exist such a path in the connectivity graph G.

The pack factor is de ned as a percentage and will arti cially limit the usage of logic resources in the FPGA. For instance, a pack factor of 100% tells the placement tool that all logic elements are available for implementation, whereas a pack factor of 50% will tell the tool that only half of the total logic resources are available. The uses for this optimization are limited but can be leveraged by advanced users. For instance, to keep a placeholder for future logic that is not included in the current ow, the pack factor can be reduced according to the estimated size. The ease of implementation will be similar to what the designer can expect when the new core is integrated. Thus, resource utilization problems may be identi ed sooner. Additionally, the pack factor can be used to determine the amount of headroom in a design, or true utilization. If there are unused logic elements, the place and route tool will be more liberal in the duplication of logic elements and the manner in which these are spread out to optimize the layout. A logic element is de ned as utilized if any portion of it is used to implement logic and not necessarily when it is fully utilized. Thus, the percentage utilization will usually be higher than the true utilization.

How much money could they possibly have I started to leave when the Brit spoke up: Hey, Banes! How about that trade today How far you think it can go You think it can get down to 12000 The round numeral, as I like to call it I don t know, I replied My target was 12080 Where s it trading now He leaned over to his keyboard and punched it in It s still hanging out in the high 2000s But I think it can make a second drop lower I m stayin in You took the trade I asked Yeah, sure I did I heard all about you You re working with Harvey, the Winklemeister Everyone here took the trade Just about every desk you see here, they all wanted to take the trade small or large, didn t matter.

Without loss of generality, let g1 , g2 , and g3 be the complete set of generic paths, as shown in Figure 617a, where the torus is represented as a unit square with its opposite sides identi ed The generic paths g1 , g2 , and g3 cut the unit square into three triangular pieces Rearrange the placements of the three pieces by identifying the opposite sides of the square in pairs along edges a and b, respectively (see Figures 617b and 617c) We thus obtain a six-gon (hexagon), with three pairs of S and T as its vertices and generic paths g1 , g2 , and g3 as its edges The hexagon presentation is called the generic form of a torus..

In other words, an FPGA that reports 60% utilization may have much more than 40% more logic resources available (ignoring the routability issues as utilization approaches 100% of course). To estimate true utilization and headroom in the design, the pack factor can be reduced until the design cannot be properly routed.

Figure 6.17 Paths g1 , g2 , and g3 constitute a complete set of generic paths. A hexagon is obtained by (a) cutting the square along g1 , g2 , and g3 , (b) pasting along b, and (c) pasting along a. (d) The resulting hexagon.