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A synthesis run that is accurate register-for-register would produce the implementation shown in Figure 14.9. Here, all logic is contained between two distinct register stages as represented in the code. If register balancing is enabled, the overall timing can be improved by moving registers into the critical path logic as shown in Figure 14.10. As can be seen from the diagram of Figure 14.10, there is no penalty in terms of latency or throughput when register balancing is used. The register utilization may increase or decrease depending on the application, and run time will be extended. Thus, if retiming is not a necessity for timing compliance, an intelligent synthesis tool will not perform these operations on noncritical paths.

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Execute a prede ned path. Find an optimal path (the shortest, or fastest, or one requiring a minimum energy, etc.). Plan a reasonable path. Plan a path that respects some constraints say, a path that would not make the robot bang into the walls of an automotive painting booth.

As with many other optimizations, the reset can have a direct impact on the ability of the synthesis tool to use register balancing. Speci cally, if two ip- ops

Robots in the factory environment tend to follow prede ned paths, sometimes with deviations allowed by their programs. Robot car painting operation is a good example. Such tasks often put a premium on path optimization: After all, in a mass production environment, shaving 1 2 sec out of a 50-sec cycle can translate into large savings. On the other hand, for a robot operating in an environment with uncertainty, optimality is ruled out and more often than not is of little concern anyway. For instance, a mobile robot that is used for food and drug delivery in a hospital is expected to go along more or less reasonable, not necessarily optimal, paths. Either of these systems can also be subject to additional constraints: For example, an arm manipulator may need to work in a narrow space between two walls.

Figure 6.2 The work space of a 3D Cartesian arm: l1 , l2 , and l3 are links; J1 , J2 , and J3 are prismatic joints; P is the arm endpoint. Each link has the front and rear end; for example, J3 is the front end of link l2 . O1 , O2 , and O3 are three physical obstacles. Also shown in the plane (l1 , l2 ) are obstacles projections. The cube abcodefg indicates the volume whose any point can be reached by the arm endpoint.

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are required to combine to balance the logic load, the two ip- ops must have the same reset state. For instance, if one reset has a synchronous reset and another an asynchronous reset (which would typically be poor design practice) or if one had a set versus a reset, the two could not be combined, and register balancing would have no effect. If this condition existed in the previous example, the nal implementation would be prevented as shown in Figure 14.11. In this implementation, the registers that drive the logic gates are initialized to an alternating 1-0-1-0 pattern. This prevents any register balancing or recombination due to incompatible register types. A smart synthesis tool may analyze the path and determine that inverting the reset type along with a corresponding inversion of the ip- op input and inversion of the ip- op output (a workaround for the offending ip- op) will improve the overall timing. However, if the delay introduced by this workaround eliminates the overall effectiveness of the register balancing, the synthesis tool will use a direct mapping and this technique will offer no signi cant optimization.